1. Field of the Invention
The present invention relates to an image sensing device and a method of adjusting a quantity of light and particularly to an image sensing device and a method of adjusting a quantity of light for sensing an image by driving, for example, an imager utilizing a CCD (Charge Coupled Device) with clocks of various frequencies to be inputted externally.
2. Description of Related Art
A so-called multi-scan type image sensing device has been proposed as an apparatus for sensing an image by driving an imager (CCD imager) utilizing a CCD with clocks of various frequencies to be inputted externally.
FIG. 10 shows an example of the structure of such as multi-scan type image sensing device. The light from an object to be picked up is incident to a lens 1 and is then received at the receiving surface of a CCD imager 3 via an iris 1A and a primary colors vertical stripe filter 2. At the light receiving surface of the CCD imager 3, a photosensor, for example, is formed and this photosensor generates charges, through photoelectric conversion, corresponding to the quantity of light received at the light receiving surface. The CCD imager 3 is driven by a driver 14 to sequentially transfer charges generated by the photosensor and moreover to convert such charges into an image signal (analog signal) as an electrical signal. This image signal is supplied to an S/H (Sample/Hold) circuit 5 after level adjustment in an AGC (Automatic Gain Controller) 4.
Here, the CCD imager 3 is designed to generate an image signal corresponding to an image, for example, of 811.times.508 pixels (number of pixels in the horizontal direction.times.number of pixels in the vertical direction) and an image displayed in field units (525/2 scanning lines) by the so-called interlaced scanning.
The S/H circuit 5 samples and holds the image signal from the AGC 4 and outputs such an image signal to an A/D converter 6 depending on the predetermined system clock supplied, for example, from an external apparatus such as a personal computer via a driver 14. The A/D converter 6 converts the image signal sampled and held by the S/H circuit 5 to the digital data of 8 bits, for example, by the A/D converting method depending on the system clock. This digital data is then supplied to a chromaticness simultaneous processing circuit 7. Here, since the light received by a CCD imager 3 is applied via the primary colors stripe filter 2, the color signals corresponding to three primary colors of the red (R), green (G) and blue (B) lights from the CCD imager 3 are outputted as the image signals. In this case, the red, green and blue color signals are outputted, for example, in the sequence of red, green, blue, red, . . . Therefore, the color signals supplied in this sequence are also outputted as the digital data in this sequence through AGC 4, S/H circuit 5 and A/D converter 6. Accordingly, the chromaticness simultaneous processing circuit 7 adjusts the output timing of the color signals of red, green and blue (so-called RGB) and simultaneously outputs such signals as a set of signals.
Namely, the chromaticness simultaneous processing circuit 7 is composed of an R data timing adjusting circuit 7R, a G data timing adjusting circuit 7G and a B data timing adjusting circuit 7B and when those obtained by converting the red, green or blue color signals into digital data with A/D converter 6 are defined respectively as R data, G data or B data, the R data timing adjusting circuit 7R, G data timing adjusting circuit 7G or B data timing adjusting circuit 7B respectively adjust the output timing of R data, G data or B data and simultaneously output respective outputs. These R data, G data and B data are supplied, for example, to external apparatus such as a personal computer and are then rendered for viewing by predetermined image processing.
Meanwhile, the system clock from an external apparatus is supplied, as explained above, not only to the A/D converter 6 and driver 14 but also to a frequency dividing circuit 8. The frequency dividing circuit 8 also has counters 9 to 11 and generates signals for giving various timings by dividing the system clock with the predetermined frequency dividing ratio.
That is, the system clock inputted to the frequency dividing circuit 8 is supplied to a counter 9. The counter 9 counts up the system clock and resets, when the count value becomes 3, the count value and outputs the pulse of the predetermined width (the width, for example, equal to the pulse width of the system clock). The counter 9 repeats the operation explained above. Therefore, the counter 9 outputs the clock (hereinafter referred to as 1/3 system clock) obtained by dividing the frequency of the system clock by 1/3.
The 1/3 system clock is supplied to the chromaticness simultaneous processing circuit 7. In this circuit, the output timings of the R data, G data and B data are adjusted on the basis of this 1/3 system clock. Moreover, this 1/3 system clock is also supplied to a counter 10. In the counter 10, the operation similar to that in the counter 9 is performed and thereby the 1/3 system clock is divided, for example, to 3/910 and is then outputted. Therefore, the counter 10 outputs the clock obtained by dividing the system clock to 1/910 (=1/3.times.3/910).
Here, the period of the clock (obtained by dividing the system clock to 1/910) outputted from the counter 10 corresponds to the length of one line (one horizontal scanning line) of the image signal outputted from the CCD imager 3. Therefore, this clock gives the horizontal scanning period for driving the CCD imager 3 and accordingly it is called as the HD (Horizontal Drive) pulse.
The HD pulse is supplied to a counter 11 and a driver 14. The counter 11 divides the HD pulse, for example, to 2/525 to output to the driver 14 by the operation similar to that in the counter 9.
Here, the period of pulse outputted from the counter 11 corresponds to one field (525/2 lines) of the image signal outputted from the CCD imager 3. Therefore, this pulse gives the vertical scanning period (field period) for driving the CCD imager 3 and accordingly it is called as the VD (Vertical Drive) pulse.
The driver 14 drives the CCD imager 3 depending on the system clock, HD pulse and VD pulse. Moreover, the driver 14 controls the S/H circuit 5 depending on the system clock.
The frequency dividing circuit 8 also generates and outputs the horizontal blanking signal (/H.BLK) and vertical blanking signal (/V.BLK) in addition to the 1/3 system clock, HD pulse, VD pulse. A manual iris adjusting mechanism 51 is operated for adjusting luminance of the image signal outputted from the CCD imager 3. That is, when the manual iris adjusting mechanism 51 is operated, an operation signal corresponding to such operation is supplied to an iris drive circuit 52. The iris drive circuit 52 drives, upon reception of the operation signal from the manual iris adjusting mechanism 51, the iris 1A corresponding to such operation signal. Thereby, the amount of light incident to the CCD imager 3 increases or decreases to adjust the luminance of the image signal outputted from the CCD imager 3.
In such a multi-scan type image sensing device as explained above, if the frequency of the system clock supplied externally is different, accumulation time for charges generated in the CCD imager 3 is also different and therefore the image having adequate luminance cannot be obtained. Namely, when the period of system clock, for example, is extremely longer or shorter, a white image or a black image has been obtained.
Therefore, as a method of obtaining the image having adequate luminance, a method for adjusting an electronic shutter has been proposed, in which the manual iris adjusting mechanism 51 is operated to adjust luminance of the image signal outputted from the CCD imager 3 or to discharge the charges generated in the CCD imager 3. This method, however, has a problem that such adjustment has been required for each change of frequency of the system clock.
Moreover, when the so-called auto-iris has been utilized, it has also been difficult to obtain the image having adequate luminance due to insufficient adjusting range since the adjusting range is usually limited to the range corresponding to the system clock with reference to use of the system clock having the predetermined and fixed period.